/*
 * File   : rx_top.v
 * Date   : 20171111
 * Author : Bibo Yang, rspwfpgas@163.com
 *
 */

`timescale 1ns/1ns
module rx_top (
    input  wire         rst,
    input  wire         clk,
	
    input  wire         phy_giga_mode,
    output wire         par_en,  // multicycle timing control signal
   
    output wire [31: 0] int_data_o,
    output wire         int_valid_o,
    output wire         int_sop_o,
    output wire         int_eop_o,
    output wire [ 1: 0] int_mod_o,

    `ifdef ENABLE_INTERNAL_PHY
    input  wire          gmii_rxclk ,
    input  wire          gmii_rxctrl,
    input  wire [ 7: 0]  gmii_rxdata
    `else
	`ifdef ENABLE_RX_GMII_SIGS	
    output wire          gmii_rxclk , 
    output wire          gmii_rxctrl,
    output wire [ 7: 0]  gmii_rxdata,
	`endif
    input  wire         rgmii_rxclk ,
    input  wire         rgmii_rxctrl,
    input  wire [ 3: 0] rgmii_rxdata
    `endif

);

`ifdef ENABLE_RX_GMII_SIGS
`else
wire          gmii_rxclk ; 
wire          gmii_rxctrl;
wire [ 7: 0]  gmii_rxdata;
`endif

`ifdef ENABLE_INTERNAL_PHY
`else
// rgmii to gmii converter
rgmii2gmii rgmii2gmii_inst(
    
    .rgmii_clk(rgmii_rxclk ),  //input  wire        
    .rgmii_den(rgmii_rxctrl),  //input  wire        
    .rgmii_din(rgmii_rxdata),  //input  wire [ 3: 0]
    
    .gmii_clk ( gmii_rxclk ),  //output wire         
    .gmii_den ( gmii_rxctrl),  //output reg         
    .gmii_din ( gmii_rxdata)   //output reg  [ 7: 0]
);
`endif

// gmii to streaming converter
rx_gearbox rx_gearbox_inst(
    .rst          (        rst  ),  //input         
    .clk          (        clk  ),  //input  wire
    
    .phy_giga_mode(phy_giga_mode),  //input 
    .par_en       ( par_en      ),  //output reg           // multicycle timing control signal
    
    .gmii_clk     ( gmii_rxclk  ),  //input  wire         
    .gmii_ctrl    ( gmii_rxctrl ),  //input  wire         
    .gmii_data    ( gmii_rxdata ),  //input  wire [ 7: 0]
                                                            
    .int_data_o   ( int_data_o  ),  //output reg  [31: 0] 
    .int_valid_o  ( int_valid_o ),  //output reg          
    .int_sop_o    ( int_sop_o   ),  //output reg          
    .int_eop_o    ( int_eop_o   ),  //output reg          
    .int_mod_o    ( int_mod_o   )   //output reg  [ 1: 0] 
);


endmodule
